
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
Preliminary Technical Data
Sample Rate Converter—Serial Output Port
For the serial output port, the frame-sync is an input and it
should meet setup and hold times with regard to SCLK on the
output port. The serial data output, SDATA, has a hold time
Table 37. ASRC, Serial Output Port
and delay specification with regard to SCLK. Note that SCLK
rising edge is the sampling edge and the falling edge is the
drive edge.
Parameter
Min
Max
Unit
Timing Requirements
t SRCSFS 1
t SRCHFS 1
t SRCCLKW
t SRCCLK
FS Setup Before SCLK Rising Edge
FS Hold After SCLK Rising Edge
Clock Width
Clock Period
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
ns
Switching Characteristics
TBD
TBD
t SRCTDD 1
Transmit Data Delay After SCLK Falling Edge
TBD
TBD
ns
t SRCTDH
1
Transmit Data Hold After SCLK Falling Edge
TBD
TBD
ns
1
AMI_DATA, SCLK, and FS can come from any of the DAI pins. SCLK and FS can also come via PCG or SPORTs. PCG’s input can be either CLKIN or any of the DAI pins.
S AMPLE EDGE
t S RCCLK
DAI_P20 - 1
( S CLK)
t S RCCLKW
t S RC S F S
t S RCHF S
DAI_P20 - 1
(F S )
t S RCTDD
DAI_P20 - 1
( S DATA)
t S RCTDH
Figure 26. ASRC Serial Output Port Timing
Rev. PrC
| Page 40 of 62 | January 2009